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FYP Part A: MRI Reconstruction on FPGA Hardware - Interim Report

Here you will find the abstract to the interim report for my Final Year Project, and the Table of Contents.

Other sections of the interim report may be put into their respective posts as individual research pieces.

As part B of my FYP commences, I will be logging the progress and challenges that arise in a separate post.


Abstract

This project outlines a solution to the increasing computational demand of Magnetic Resonance (MR) image reconstruction, and the limitations of general-purpose Central Processing Units (CPUs) and Graphics Processing Units (GPUs) in meeting the low latency demands of clinical imaging.

The conducted literature review establishes cartesian k-space sampling and the Fast Fourier Transform (FFT) as the most appropriate reconstruction framework for a proof-of-concept hardware implementation. This FFT approach, coupled with Finite Impulse Response (FIR) low-pass filtering in the k-space domain, is the preferred pre-processing approach to demonstrate the versatility of specialised hardware.

The target platform is the Terasic Cyclone V GX Starter Kit, featuring the Cyclone V GX 5CGXFC5C6F27C7N FPGA, whose dedicated DSP blocks and embedded M10K memory resources are well-suited to the pipelined FFT and FIR workloads required. Hardware resource analysis shows that the complete reconstruction pipeline (comprising of a UART receive buffer, symmetric FIR filter, row-wise IFFT, matrix transposition, and column-wise IFFT) consumes fewer than 12 of the 150 available DSP blocks across target resolutions ranging from 64×64 to 256×256, demonstrating substantial headroom for future extension.

Communication to the host device is achieved through an Adafruit FT232H breakout board over GPIO, providing up to 1.2 MB/s throughput in Virtual COM Port (VCP) mode via MATLAB’s serialport() function. The reconstructed output is evaluated against a reference image produced in MATLAB software, using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM) to assess the effect of hardware filtering and acceleration on image quality.


Table of Contents

This table of contents serves as a visualisation of the topics covered in the interim report of my final year project. Please contact me if you wish to read the full paper.

  • Abstract
  • Acknowledgements
  • Contributions
  • Table of Contents
  • List of Figures
  • List of Tables
  • Nomenclature
  • Chapter 1: Introduction
    • 1.1 Project Motivation
      • 1.1.1 Latency in Reconstruction
      • 1.1.2 Limitations of General-Purpose Computing
    • 1.2 Project Objective
  • Chapter 2: Literature Review
    • 2.1 Overview of the MRI Reconstruction Pipeline
    • 2.2 MRI Data Acquisition
      • 2.2.1 Sampling Trajectory
        • 2.2.1.1 Cartesian
        • 2.2.1.2 Radial
        • 2.2.1.3 Spiral
      • 2.2.2 K-Space Representation
      • 2.2.3 Frequency Sampling (Over/Under)
    • 2.3 Image Processing
      • 2.3.1 Processing in K-Space
      • 2.3.2 Quantitative Spatial Image Analysis
        • 2.3.2.1 PSNR
        • 2.3.2.2 Structural Similarity Index (SSIM)
    • 2.4 Image Reconstruction
      • 2.4.1 Fast Fourier Transform (FFT)
      • 2.4.2 Non-Uniform Fast Fourier Transform (NUFFT)
  • Chapter 3: FPGA Architecture
    • 3.1 Overview
    • 3.2 Interconnects
      • 3.2.1 Row / Column Interconnect
      • 3.2.2 Local Interconnect
      • 3.2.3 Direct Link Interconnect
    • 3.3 Memory Architecture
    • 3.4 Lookup Tables (LUTs)
    • 3.5 Intellectual Property (IP) Blocks
    • 3.6 Digital Signal Processing (DSP) Block
      • 3.6.1 FFT and FIR Filtering in Hardware
  • Chapter 4: Software Architecture
    • 4.1 Overview
    • 4.2 Verilog HDL
      • 4.2.1 Behavioural and Structural Descriptions
    • 4.3 Development Environments
    • 4.4 Data Interfacing with FPGA
  • Chapter 5: System Design
    • 5.1 Development Workflow
      • 5.1.1 IP Core Access & Licensing
    • 5.2 Communication Interfaces
      • 5.2.1 Option A: UART
      • 5.2.2 Option B: UART (Reduced Dataset) and JTAG
      • 5.2.3 Option C: PCIe 2.0 (Hard IP) & HSMC
      • 5.2.4 Option D: Parallel Serial Communications through GPIO
      • 5.2.5 Discussion
    • 5.3 Resource Requirements and Throughput Analysis
      • 5.3.1 FFT IP Core Resource Characterisation
      • 5.3.2 Two-Dimensional Reconstruction Resource Budget
      • 5.3.3 Throughput and Frame Rate Analysis
    • 5.4 Pre-Processing: K-Space FIR Filter Design
    • 5.5 Pipelining Strategy
    • 5.6 MATLAB Reference and Evaluation
  • Chapter 6: Conclusion
    • 6.1 Proposed Timeline for Implementation
  • References
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